Due to recent spread of CDs and DVDs, it is ordinary for an individual person to record a large amount of information on an optical disk medium or reproduce information from the optical disk medium. These digital data are recorded as a minute mark train along with a guide groove of a spiral shape formed on the optical disc medium. Upon reproducing the data, a reflected light, i.e., laser beam irradiated onto and reflected from the medium surface is converted into an electric signal (referred to as reproduced signal hereinafter), to which a variety of filtering processings or decoding processings are applied to thereby create a 1-bit digital information train.
In order to obtain a 1-bit digital information train from the reproduced signal, it is needed to first extract a clock in synchrony with the reproduced signal from the reproduced signal. This is because a deviation of central axis etc. of the disk slightly deviates the channel route of the reproduced signal even if the rotation of the spindle is correct, to thereby deviate the position to be identified if a fixed-frequency clock timing is employed. For this reason, the clock in synchrony with the reproduced signal is extracted by using a circuit referred to as PLL (phase locked loop). The reproduced signal is binarized and extracted at this synchronizing timing by using, for example, a specific threshold, to obtain the 1-bit digital information train. This digital information train is demodulated, and thereafter subjected to error correction etc. to finally provide the image and/or music information.
An ordinary PLL has a basic configuration including three elements including a phase comparator, a loop filter, and a voltage-controlled oscillator (VCO). In the PLL, the phase comparator generates a phase difference between the input signal and an output of the VCO, the loop filter removes harmonic components and noise component in the phase difference, and a feedback loop that controls the frequency of the VCO is formed based on the output of the loop filter. This feedback loop allows the output of the VCO to operate in synchrony with the input signal.
Assuming that the transfer characteristics of the phase comparator, loop filter and VCO are Kp, F(s) and Kv/s, respectively, the open-loop transfer characteristic G(s) of the PLL is expressed by the following formula (1):G(s)=Kp·Kv·F(s)/s  (1)The closed-loop transfer characteristic H(s) thereof is expressed by the following formula (2):H(s)=G(s)/(1+G(s))  (2)If the open-loop characteristic G(s) is of a first order, there is no frequency pull-in stage, whereby the pull-in range is narrow, and both the quick response and low jitter cannot be satisfied. For this reason, a secondary- or higher-order characteristic is employed for the transfer characteristic F(s) of the loop filter by using a lag-lead filter etc. Note that the loop characteristic is determined by resistors, capacitors etc. in many cases.
In the conventional analog PLL technique, it is difficult to mass-produce the PLLs having a uniform loop characteristic due to the factor that the characteristic, changes depending on the range of variety of parts and ambient temperature. In addition, there is a problem in the analog PLL that the characteristic degradation due to variation with time is unavoidable. There is digital PLL as the PLL that can avoid such a problem. The digital PLL is described in, for example, Patent Publication-1.
FIG. 11 shows the configuration of a reproducing apparatus that includes a conventional digital PLL. In the reproducing apparatus 500, an analog signal read from the optical disc etc. is sampled in synchrony with a system clock of a fixed frequency by an A/D converter 501. An interpolator 502 calculates, based on the PLL-clock-phase signal output from a PLL-clock-phase signal generator 506, a sampled value of the reproduced signal upon deviation of the sampling phase from the sampled values output from the A/D converter 501, by using a linear interpolation. A phase error detector 504 calculates phase shift information from the interpolated value output from the interpolator 502. This phase shift information is input to a loop filter 505 for suppression of the high frequency components, and thereafter input to the PLL-clock-phase signal generator 506.
The PLL-clock-phase signal generator 506 generates a PLL-clock-phase signal of a saw-tooth waveform based on the output of the loop filter 505. By controlling the phase of interpolator 502 based on this PLL-clock-phase signal, the interpolator 502 generates an interpolated value corresponding to the sampled value of read signal that is in synchrony with the channel clock. The interpolated value output from the interpolator 502 is input to a binarization circuit 503, and the recorded information is detected by the binarization circuit 503.
In the above configuration, the phase of sampling clock of the A/D converter 501 and the phase of channel clock of the read signal are independent of each other, and feedback of the PLL-clock-phase signal to the interpolator 502 allows the interpolator 502, phase error detector 504, loop filter 505, and PLL-clock-phase signal generator 506 to configure a PLL loop. This configuration allows those elements including an oscillator to be digitalized, whereby PLLs having the same characteristic and a higher resistance to the ambient change can be mass-produced. In addition, although it has been difficult to manufacture a PLL having a wider capture range because the analog VCO is non-linear, i.e., Kv is a non-linear function of “s”, this digitalization will solve the above problem.
Next, disk rotational control will be described. There are mainly two techniques for the rotational control of a disk: a CLV (constant linear velocity) control technique that maintains the linear velocity constant, and a CAV (constant angular velocity) control technique that fixes the rotational angular velocity. It is assumed here that recording is performed on the medium, such as CD or DVD, at a constant linear density. In the CLV control, since the rotational speed of spindle changes by about 2.4 times between the inner periphery and the outer periphery, there arise problems that a random access is accompanied by a waiting time for the spindle control and that this causes a large amount of power dissipation. On the other hand, in the CAV control, since the spindle is rotated at a constant velocity, the waiting time needed for the rotational control is zero to thereby improve the accessibility. Due to these reasons, the number of apparatuses using the CAV control is increasing. However, if a disk on which recording is performed using the CLV control is subjected to the CAV control, the synchronizing clock frequency of the reproduced signal changes by about 2.4 times between the inner periphery and the outer periphery, to thereby require a PLL having wider lock range and capture range.
The phase comparator in the PLL detects the phase difference between the clock timing of the internal oscillator and the signal obtained by comparing the input signal against a specific threshold. The reproduced signal from the optical disk has a smaller slope of the edge for a higher recording density, due to the characteristic of the transmission path between the disk medium and the pickup. Thus, a deviation of the threshold for the comparison, if occurs, involves a phase deviation in the result of phase comparison, thereby causing a statistic phase error in the output synchronizing clock. The occurrence of phase deviation involves a deviation of the identification position for the data, whereby the statistic phase error increases the possibility of occurrence of an error in the identification of data.
The deviation of comparison threshold occurs mainly due to a low-frequency component included in the reproduced signal. The low-frequency fluctuation in the recorded code itself is avoided by providing a plurality of synchronizing patterns inserted periodically, and recording a synchronizing pattern that is selected so that the ratio of number of “0s” to number of “1s” right before the synchronizing pattern assumes a constant. However, this technique cannot completely suppress the low-frequency fluctuation, whereby a fluctuation occurs due to a disturbance of the positional control system for the reading-use beam, a defect on the disk etc.
In order to solve the problem of the above fluctuation, it is common to provide a HPF (high-pass-filter) on the preceding stage of the PLL for adding thereto the function of removing the noise of a low-frequency range (for example, refer to Patent Publication-2). FIG. 12 shows the configuration of the information reproducing apparatus described in Patent Publication-2. An analog signal read from an optical disc etc. is sampled by an A/D converter 511 at a clock timing generated by a VCO 518. The sampled value is input to a DC feedback circuit 512 for suppressing a DC fluctuation. Thereafter, it is input to a phase error detector 515 for generation of a phase error, and a high-frequency component is removed therefrom by a next-stage loop filter 516, to thereby output digital frequency information.
The digital frequency information output from the loop filter 516 is converted into an analog signal by a D/A converter 517, to control the oscillation frequency of the VCO 518. Operation of the A/D converter 511 based on the synchronizing clock output from the VCO 518 and control of the sampling phase of the A/D converter 511 by using the VCO 518 provides a PLL loop including the A/D converter 511 and DC feedback circuit 512. The output of DC feedback circuit 512 is input to a PR (partial-response) equalizer 513, and subjected to equalization to a desired PR channel. Thereafter, information of thereof is detected by a maximum-likelihood detector 514 by using this channel characteristic. In the information reproducing apparatus 510, addition of the HPF function, such as a DC feedback, before performing the phase comparison provides a stability for the phase synchronization characteristic without being affected by the DC level fluctuation, whereby stable information reproduction is achieved. Provision of the HPF on the preceding stage of the PLL also provides a similar effect.
Here, a higher cutoff frequency of the HPF provides a higher attenuation rate in the low-frequency range, to raise the stability of the PLL against the noise of low frequency band. However, an excessively higher cutoff frequency of the HPF raises the sensitivity to noise of higher frequency band on the contrary, thereby increasing jitter of the PLL synchronizing clock to cause an out-of-synchronization. Therefore, there is an optimum solution for the cutoff frequency of HPF. The low-frequency-band noise superimposed on the reproduced signal from the optical disc mostly depends on the information and shape of the medium surface, and includes mostly a component that is proportional to the ratio of the reproducing speed to the nominal speed. Therefore, there exists an optimum solution for the cutoff frequency of HPF with respect to the reproducing speed ratio. In the case of reproduction using the CAV technique, the disk linear speed changes by about 2.4 times between the inner periphery and the outer periphery, and thus in the reproduction using the CLV technique as well, a countermeasure for a speed change of 2.42=5.8 times is needed in the case of reproducing before the spindle assumes a lower speed just after a long seeking operation. In these cases, it is preferable to change the cutoff frequency of HPF provided on the preceding stage of the PLL in accordance with the speed ratio.    Patent Publication-1: JP-1998-27435A    Patent Publication-2: JP-2006-40458A
The Information reproducing apparatus 510 described in Patent Publication-2 is configured as a phase synchronization loop including a HPF (DC feedback circuit 512). For this reason, the HPF having a digital configuration operates based on the clock that is in synchrony with the input signal, and the loop characteristic also changes depending on the speed ratio. However, in the information reproducing apparatus 510 described in Patent Publication-2, insertion of the HPF in the PLL loop increases the loop delay of the PLL, to thereby incur the problem that the tracking performance of the PLL is degraded. Improvement of the tracking performance may be achieved by raising the loop band of the PLL; however, there arise the problem of weakness against noise in such a case. In the case of a configuration wherein the HPF is provided outside the PLL loop, the delay of PLL loop may be alleviated; however, the HPF loop characteristic in accordance with the speed ratio cannot be assured.